CDCS504TPWRQ1

CDCS504-Q1 Clock Buffer/Clock Multiplier

Texas Instruments CDCS504-Q1 Clock Buffer/Clock Multiplier is a LVCMOS input clock buffer with selectable frequency multiplication. The CDCS504-Q1 has an output enable pin. The device accepts a 3.3V LVCMOS signal at the input. The input signal is processed by a phase-locked loop (PLL), whose output frequency is either equal to the input frequency or multiplied by the factor of four. By this, the device can generate output frequencies between 2MHz and 108MHz. A separate control pin can be used to enable or disable the output. The CDCS504-Q1 device operates in a 3.3V environment.