TPS51200DRCR

Texas Instruments
595-TPS51200DRCR
TPS51200DRCR

製造商:

說明:
功率管理專用 - PMIC Sink/Source DDR Term Reg A 595-TPS51200D A 595-TPS51200DRCT

ECAD模型:
下載免費的庫載入器,為ECAD工具轉換此文件。瞭解更多關於 ECAD 型號的資訊。

庫存量: 2,943

庫存:
2,943
可立即送貨
在途量:
26,500
預期2026/4/23
34,900
預期2026/4/27
工廠前置作業時間:
12
工廠預計生產時間數量大於所顯示的數量。
最少: 1   多個: 1
單價:
NT$-.--
總價:
NT$-.--
估計關稅:
包裝:
完整捲(訂購多個3000)

Pricing (TWD)

數量 單價
總價
零卷 / MouseReel™
NT$31.91 NT$31.91
NT$22.76 NT$227.60
NT$20.54 NT$513.50
NT$18.03 NT$1,803.00
NT$16.85 NT$4,212.50
NT$16.17 NT$8,085.00
NT$15.56 NT$15,560.00
完整捲(訂購多個3000)
NT$14.81 NT$44,430.00
NT$14.45 NT$86,700.00
† NT$215.00 MouseReel™費用將加入您的購物車內並自動計算。所有MouseReel™訂單均不能取消和不能退換。

備用包裝

製造商 元件編號:
包裝:
Reel, Cut Tape, MouseReel
供貨情況:
庫存量
價格:
NT$38.36
最小值:
1

商品屬性 屬性值 選擇屬性
Texas Instruments
產品類型: 功率管理專用 - PMIC
RoHS:  
TPS51200
Voltage Regulator, Multiple Outputs
SMD/SMT
VSON-10
3 A
3.5 V
1.1 V
1.25 V
- 40 C
+ 85 C
1 uA
Reel
Cut Tape
MouseReel
應用: Memory Termination Regulator, Notebooks, Telecom, Copiers and Printers
品牌: Texas Instruments
組裝國家: Not Available
擴散國: US
原產國: PH
開發套件: TPS51200EVM
輸入電壓范圍: 1.1 V to 3.5 V
濕度敏感: Yes
運作供電電流: 700 uA
工作電源電壓: 2.375 V to 3.5 V
輸出電壓范圍: 600 mV to 1.25 V
Pd - 功率消耗 : 1.92 W
產品類型: Power Management Specialized - PMIC
原廠包裝數量: 3000
子類別: PMIC - Power Management ICs
每件重量: 26.100 mg
找到產品:
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所選屬性: 0

此功能需要啟用JavaScript。

CNHTS:
8542399000
CAHTS:
8542390000
USHTS:
8542390090
JPHTS:
8542390990
TARIC:
8542399000
MXHTS:
8542399999
ECCN:
EAR99

TPS51200 Sink/Source DDR Termination Regulator

Texas Instruments TPS51200 Sink/Source DDR Termination Regulator is specifically designed for low-input voltage, low-cost, low-noise systems where space is a crucial consideration. The TPS51200 maintains a fast transient response and only requires a minimum output capacitance of 20µF. The TPS51200 supports a remote sensing function. This device also supports all power requirements for DDR, DDR2, DDR3, Low-Power DDR3, and DDR4 VTT bus termination. The Texas Instruments TPS51200 provides an open-drain PGOOD signal to monitor the output regulation and an EN signal that can be used to discharge VTT during S3 (suspend to RAM) for DDR applications.