UF3C065040K3S

Name: onsemi UF3C065040K3S
Brand: onsemi
SKU: 431-UF3C065040K3S
Price: 699.43 TWD
Availability: InStock

影像僅供參考
請參閱產品規格

Mouser 編號：

431-UF3C065040K3S

製造商編號：

UF3C065040K3S

製造商：

onsemi

說明：

碳化矽MOSFET 650V/40MOSICFETG3TO247-3

規格書:

UF3C065040K3S 規格書 (PDF)

ECAD模型:

下載免費的庫載入器，為ECAD工具轉換此文件。瞭解更多關於 ECAD 型號的資訊。

更多資訊

瞭解更多關於onsemi UF3C065040K3S的資訊

.hidden-for-nojs { display: none; } .pull-right-nojs { justify-content: flex-end; }

商品屬性	屬性值	選擇屬性
製造商:	onsemi
產品類型:	碳化矽MOSFET
RoHS:
安裝風格:	Through Hole
封裝/外殼:	TO-247-3
通道數:	1 Channel
Vds - 漏-源擊穿電壓:	650 V
Id - C連續漏極電流:	54 A
Rds On - 漏-源電阻:	42 mOhms
Vgs - 閘極-源極電壓:	- 25 V, + 25 V
Vgs th - 門源門限電壓 :	4 V
Qg - 閘極充電:	51 nC
最低工作溫度:	- 55 C
最高工作溫度:	+ 175 C
Pd - 功率消耗 :	326 W
通道模式:	Enhancement
資格:	AEC-Q101
公司名稱:	SiC FET
品牌:	onsemi
配置:	Single
封裝:	Tube
產品類型:	SiC MOSFETS
系列:	UF3C
原廠包裝數量:	30
子類別:	Transistors
晶體管極性:	N-Channel
每件重量:	6 g

找到產品:

若要顯示類似商品，請選取至少一個核選方塊

至少選中以上一個核取方塊以顯示在此類別中類似的產品。

所選屬性: 0

篩選文檔:

規格書

UF3C065040K3S 規格書 (PDF)

Models

SPICE Model/UF3C065040K3S (文字)

PCN

合規守則

CNHTS:: 8541290000
USHTS:: 8541290065
ECCN:: EAR99

原產地分類

原產國:: 菲律賓
封裝原產國:: 中國
擴散國:: 美國

出貨時，國家可能會有所變更。

UF3C SiC FETs

onsemi UF3C High-Performance SiC FETs are cascode Silicon Carbide (SiC) products that co-package high-performance G3 SiC JFETs with a cascode-optimized Si MOSFET to produce a standard gate drive SiC device. This series exhibits ultra-low gate charge and is excellent for switching inductive loads and applications requiring a standard gate drive. The onsemi UF3C SiC FETs are available in 650V, 1200V, and 1700V versions and are offered in D²PAK-3, D²PAK-7, D²PAK-7L, TO-247-3L, TO-247-4L, and TO-220-3L packages.

High-Performance SiC FETs

onsemi High-Performance SiC FETs deliver best-in-class switching speed, lower switching losses, higher efficiency, and excellent cost-effectiveness. The components are offered in standard thru-hole (including Kelvin) and surface mount packages. The family comprises the UF4C/SC, UJ4C/SC, UJ3C, and UF3C/SC series and is based on a unique cascode configuration, where a high-performance SiC JFET is co-packaged with a cascode-optimized Si-MOSFET to produce a standard gate drive SiC device.