STEF512PUR

STMicroelectronics
511-STEF512PUR
STEF512PUR

製造商:

說明:
熱插拔電壓控制器 Dual electronic fuse (eFuse) for 5 V and 12 V rails

ECAD模型:
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供貨情況

庫存:
暫無庫存
工廠前置作業時間:
24 週 工廠預計生產時間。
最少: 5000   多個: 5000
單價:
NT$-.--
總價:
NT$-.--
估計關稅:
此產品免費航運

Pricing (TWD)

數量 單價
總價
完整捲(訂購多個5000)
NT$27.44 NT$137,200.00

商品屬性 屬性值 選擇屬性
STMicroelectronics
產品類型: 熱插拔電壓控制器
RoHS:  
Reel
品牌: STMicroelectronics
產品類型: Hot Swap Voltage Controllers
原廠包裝數量: 5000
子類別: PMIC - Power Management ICs
每件重量: 25 mg
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所選屬性: 0

CNHTS:
8542399000
USHTS:
8542390090
ECCN:
EAR99

STEF512PUR Dual Electronic Fuse

STMicroelectronics STEF512PUR Dual Electronic Fuse is designed to protect circuitry on the output from overcurrent and overvoltage events in applications requiring hot-swap operation and in-rush current control. The STEF512PUR embeds two independent electronic fuses, one for 5V rails and one for 12V rails. Due to the very low ON-resistance of the integrated power FETs, the voltage drop from the main supply to the load is very low during normal operation. The user can adjust the startup time via two small soft-start capacitors, connected to the relevant pins. In this way, the inrush current at startup can be kept under control. The maximum load current of the STEF512PUR is precisely limited by utilizing a sense FET topology, to factory-defined values of 3A for a 5V output and 4A for a 12V output.

LM5060 High-Side Protection Controllers

Texas Instruments LM5060 High-Side Protection Controllers with Low Quiescent Current offers intelligent control of a high-side N-channel MOSFET during normal on/off transitions and fault conditions. The constant rise time of the output voltage results from the inrush current control. Both an Input UVLO (with hysteresis) and a programmable input OVP are provided, with an enable input offering a remote on or off control. The initial start-up VGS fault detection delay time, the transition VDS fault detection delay time, and the continuous over-current VDS fault detection delay time is programmed from a single capacitor. The MOSFET is latched off until either the enable input, or the UVLO input is toggled low and then high when a detected fault condition persists longer than the allowed fault delay time.