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Alliance Memory 2GB/4GB/8GB/16GB/32GB LPDDR4 SDRAM

Alliance Memory 2GB/4GB/8GB/16GB/32GB LPDDR4 SDRAM is organized as 1 or 2 channels per device, and the individual channel is 8-banks and 16-bits. This product uses a double-data-rate architecture to achieve high-speed operation. The double data rate architecture is a 16n prefetch architecture with an interface. It's designed to transfer two data words per clock cycle at the I/O pins. These devices offer fully synchronous operations referenced to the rising and falling edges of the clock. The data paths are internally pipelined and 16n bits prefetched to achieve very high bandwidth.

Features

  • Configuration
    • 32x for 2-channels per device (AS4C64M32MD4, AS4C128M32MD4, AS4C256M32MD4, AS4C512M32MD4, AS4C1G32MD4)
    • 16x for 1-channel per device (AS4C128M16MD4, AS4C256M16MD4)
    • 8x internal banks per channel
  • On-chip ECC
    • Single-bit error correction (per 64-bits); maximizes reliability
    • Optional ERR output signal per channel, which indicates ECC event occurrence
    • ECC register controls ECC function
  • Low-voltage core and I/O power supplies, VDD2 /VDDQ = 1.06/1.17V, VDD1 = 1.70V to 1.95V
  • Low Voltage Swing Terminated Logic (LVSTL) I/O interface
  • Internal VREF and VREF training
  • Dynamic ODT
    • DQ ODT: VSSQ termination
    • CA ODT: VSS termination
  • Selectable output drive strength (DS)
  • 1.6GHz maximum clock frequency (3.2Gbps for one channel)
  • 16-bit pre-fetch DDR data bus
  • Single data rate (multiple cycles) command/address bus
  • Bidirectional/differential data strobe per byte of data (DQS, DQS)
  • DMI pin support for write data masking and DBI functionality
  • Programmable READ and WRITE latencies (RL/WL)
  • Programmable and on-the-fly burst lengths (BL =16, 32)
  • Support non-target DRAM ODT control
  • Directed per-bank refresh for concurrent bank operation and ease of command scheduling
  • ZQ calibration
  • -40°C to +105°C operation temperature (automotive A2)
  • On-chip temperature sensor to control self-refresh rate; status can be read from MR4
  • Packages
    • 2Gb/4Gb/: 200 ball FBGA (10mm x 14.5mm x 0.8mm)
    • 8Gb: 200 ball FBGA (10mm x 14.5mm x 1.1mm)
  • RoHS-compliant, Green packaging

Block Diagram

Alliance Memory 2GB/4GB/8GB/16GB/32GB LPDDR4 SDRAM
Alliance Memory 2GB/4GB/8GB/16GB/32GB LPDDR4 SDRAM
View Results ( 6 ) Page
零件編號 規格書 存儲容量 數據匯流排寬度 組織
AS4C256M32MD4V-062BAN AS4C256M32MD4V-062BAN 規格書 8 Gbit 32 bit 256 M x 32
AS4C1G32MD4V-046BIN AS4C1G32MD4V-046BIN 規格書 32 Gbit 32 bit 1 G x 32
AS4C512M32MD4V-046BIN AS4C512M32MD4V-046BIN 規格書 16 Gbit 32 bit 512 M x 32
AS4C128M16MD4-062BAN AS4C128M16MD4-062BAN 規格書 2 Gbit 16 bit 128 M x 16
AS4C256M16MD4-062BAN AS4C256M16MD4-062BAN 規格書 4 Gbit 16 bit 256 M x 16
AS4C128M32MD4-062BAN AS4C128M32MD4-062BAN 規格書 4 Gbit 32 bit 128 M x 32
發佈日期: 2020-12-08 | 更新日期: 2024-05-07