The AD9139 TxDAC+® includes features optimized for wideband communication applications, including 1× and 2× interpolation, a Delay-Locked Loop (DLL) powered high-speed interface, sample error detection, and parity detection. A 3-wire serial port interface provides for the programming/readback of many internal parameters. A full-scale output current can be programmed over a range of 9mA up to 33mA. The AD9139 is ideal for wideband communications, transmit diversity/MIMO, instrumentation, and automated test equipment.
Features
- <2 DAC clock cycles very small inherent latency variation
- Proprietary low spurious and distortion design
- 6-carrier GSM ACLR = 79dBc at 200MHz IF
- SFDR >85dBc (bandwidth = 300MHz) at zero ZIF
- Flexible 16-bit LVDS interface
- Supports word and byte load
- Multiple chip synchronization
- Fixed latency and data generator latency compensation
- Selectable 1× or 2× interpolation filter
- Support input signal bandwidth up to 575MHz
- High performance, low noise PLL clock multiplier
- Digital inverse sinc filter
- 700mW at 1230MSPS Low power
- FIFO eases system timing and includes error detection
Applications
- Wireless communications
- 3G/4G and MC-GSM base stations
- Wideband repeaters
- Software-defined radios
- Wideband communications
- Point-to-point
- LMDS/MMDS
- Transmit diversity/MIMO
- Instrumentation
- Automated test equipment
Functional Block Diagram
發佈日期: 2014-01-23
| 更新日期: 2022-03-11

