Diodes Incorporated PI7C9X3G1632GP PCIe3.0 Packet Switch
Diodes Incorporated PI7C9X3G1632GP PCIe3.0 Packet Switch supports 32 lanes of GEN3 SERDES in flexible 2-port to 16-port configurations. The architecture of the PCIe packet switch allows the flexible port configuration by allocating variable lane width for each port. A basic cell of the switch architecture is called a tile, which consists of 8 ports and 16 lanes. The PI7C9X3G1632GP is built with 2 tiles connected by internal signal paths.Features
- Port and Lane Configurations for 16-port/32-Lane PCI Express GEN3 packet switch
- Configurable Upstream port number up to 2
- Configurable Upstream lane widths of x1, x2, x4, x8 or x16
- Configurable Downstream port numbers up to 15
- Configurable Downstream lane widths of x1, x2, x4, x8 or x16
- Reference Clock Management
- Integrated PCIe Gen3 clock buffer for all downstream ports
- Support three reference clock structures (Common, SRNS, and SRIS)
- Handle SSC Isolation up to three ports
- Provide two clock application modes (Base and CDSR)
- Power Management
- Support 7 power states (P0/P0s/P1/P1.1/P1.2/P2/P1.2PG)
- Start-up power management scheme
- “Empty” Hot-Plug ports put in P2 state
- Continuous power management scheme
- Support ASPM L1 Sub-state (P1.1/P1.2)
- PHY and MAC Layers
- PHY initial settings optionally programmable through JTAG, EEPROM, and SMBus/I2C
- Adaptive Continuous Time Linear Equalizer and 5-tap Decision Feedback Equalizer for RX
- Adaptive and programmable 3-tap TX equalization
- RX Polarity Inversion and Lane Reversal
- Data Link Layer
- Programmable ACK latency timer to respond ACK based upon traffic condition
- Configurable Flow Control Credit to balance bandwidth utilization and buffer usage
- Transaction Layer
- Packet forwarding options including Cut-Through and Store & Forward
- Support up to 512-Byte Max Payload Size
- Low packet forwarding latency < 150ns (typical case)
- Access Control Service (ACS) for peer-to-peer traffic
- Address Translation (AT) packet for SR-IOV application
- Support Atomic operation
- Support Multicast
- Provide Performance Visibility for ingress/egress packet types and packet counts
- Multi-Host Application
- Support up to 3 Cross-Domain End-Point (CDEP) ports for Host-to-Host Communications
- Support Fail-over using CDEP port
- Provide up to 8 physical or 16 virtual DMA channels enabling communications among Hosts and EPs
- Switch bifurcated up to 2 individual packet switches to allow 2 hosts to operate independently
- Reliability, Availability, and Serviceability
- Enhanced Advanced Error Reporting
- End-to-End Data Protection with ECC
- Error Handling Mechanism
- Support Surprise Hot Removal
- Supports Downstream Port Containment (DPC)
- Support Hot Plug for Upstream and Downstream port
- Provide Serial and Parallel Hot Plug Types
- Support LED Management
- Thermal Sensor reporting operational temperature instantly
- IEEE 1149.1 and 1149.6 JTAG interface support
- Advanced Diagnostic Tools
- PHY EyeTM
- MAC ViewerTM (including embedded LA)
- PCIBUDDYTM
- On-Line PRBS loopback test
- On-Line Compliance pattern test
- Side-band Management Interface
- I2C/SMBUS/JTAG
- SPI EEPROM
- Standard Compliance
- Compliant with PCI Express Base Specification Revision 3.1
- Compliant with PCI Express CEM Specification Revision 3.0
- Compliant with Advanced Configuration Power Interface (ACPI) Specification
- Compliant with System Management (SM) Bus, Version 2.0
- Power and Package
- Two power rails (0.95V and 1.8V)
- Power consumption: 5.6W under full loaded condition
- Totally Lead-Free & Fully RoHS Compliant
- Halogen and Antimony Free Green Device
- For automotive applications requiring specific change control (i.e. parts qualified to AEC-Q100/101/104/200, PPAP capable, and manufactured in IATF 16949 certified facilities), please contact us or your local Diodes representative. https://www.diodes.com/quality/product-definitions/
- Packages: 676 HFCBGA 27mm X 27mm
- Operating Ambient Temperature
- Support Industrial Temperature Range -40o to 85oC
發佈日期: 2022-06-09
| 更新日期: 2025-10-10
