ROHM Semiconductor I²C & Microwire Bus EEPROMs

Rohm's I²C Bus EEPROMs completely conform to the standard I²C BUS, with all controls available from the SCL and SDA ports. A low current consumption and voltage range from 1.6 to 5.5V make these EEPROMs most suitable for use in battery-powered applications. Rohm's MicroWire EEPROMs offer high-speed write (5ms max) an address auto-increment function at read operation, and a write mistake prevention function. These EEPROMs feature up to 1 million write cycles and more than 40 years of data retention. They are available in a wide variety of package styles, from large robust packages to small packages designed for a minimal PCB footprint.

Features

  • I2C EEPROM
  • All controls available by 2 ports of serial clock(SCL) and serial data(SDA)
  • Other devices than EEPROM can be connected to the same port, saving microcontroller port
  • 1.6V to 5.5V single power source action most suitable for battery use
  • 1MHz action is possible (1.7V to 5.5V)
  • Up to 8 bytes in page write mode
  • Self-timed programming cycle
  • Low current consumption
  • Prevention of write mistake
  • Write (write protect) function added
  • Prevention of write mistake at low voltage
  • More than 1 million write cycles
  • More than 40 years data retention
  • Noise filter built in SCL / SDA terminal
  • Initial delivery state FFh
  • MicroWire EEPROM
  • 3-line communications of chip select, serial clock, serial data input/output (the case where input and output are shared)
  • Operations available at high-speed 3MHz clock (4.5V ~ 5.5V)
  • High speed write available (write time 5ms max.)
  • Same package and pin configuration from 1Kbit to 16Kbit
  • 1.7~5.5V single power source operation
  • Address auto-increment function at read operation
  • Write mistake prevention function
    • Write prohibition at power on
    • Write prohibition by command code
    • Write mistake prevention function at low voltage
  • Self-timed programming cycle
  • Program condition display by READY / BUSY
  • More than 40 years of data retention
  • More than 1 million write cycles
  • Initial delivery state all addresses FFFFh
發佈日期: 2014-09-11 | 更新日期: 2024-02-05