Texas Instruments SN74LV8T164/SN74LV8T164-Q1 Shift Register

Texas Instruments SN74LV8T164/SN74LV8T164-Q1 Parallel-Load Shift Register contains an 8-bit shift register with asynchronous clear (CLR) input and AND-gated serial inputs. The gated serial (A and B) inputs permit complete control over incoming data. A low at either input inhibits new data entry and resets the first flip-flop to the low level at the next clock (CLK) pulse. A high-level input enables the other input, determining the first flip-flop's state. The data at the serial inputs can be changed while CLK is low or high, provided the minimum set-up time requirements are met. Clocking occurs on the low-to-high-level transition of CLK.

The input is designed with a reduced threshold circuit to support up translation when the supply voltage is larger than the input voltage. The 5V tolerant input pins also enable down translation when the input voltage is larger than the supply voltage. The output level always references the supply voltage (V_CC) and supports 1.8V, 2.5V, 3.3V, and 5V CMOS levels. The SN74LV8T164-EP devices have gold bond wires, a temperature range of –55 to +105°C, and an SnPb lead finish. The Texas Instruments SN74LV8T164-Q1 devices are AEC-Q100 qualified for automotive applications.

Features

Latching logic with a known power-up state provides consistent start-up behavior
Wide operating range of 1.65V to 5.5V
5.5V tolerant input pins
Single-supply voltage translator (refer to LVxT Enhanced Input Voltage)
Up translation
- 1.2V to 1.8V
- 1.5V to 2.5V
- 1.8V to 3.3V
- 3.3V to 5.0V