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Texas Instruments TMS320C5517 Fixed-Point Digital Signal Processor

Texas Instruments TMS320C5517 Fixed-Point Digital Signal Processor (DSP) is based on the core TMS320C55x DSP generation CPU processor. The C55x DSP architecture achieves high performance and low power through increased parallelism and a total focus on power savings. The CPU supports an internal bus structure that is composed of one program bus, one 32-bit data read bus and two 16-bit data read buses, and two 16-bit data write buses. The device also has additional buses dedicated to peripheral and DMA activity. These buses provide the ability to perform up to four 16-bit data reads, and two 16-bit data writes in a single cycle. The device also includes four DMA controllers, each with four channels, providing data movement for 16 independent channel contexts without CPU intervention. Each DMA controller can perform one 32-bit data transfer per cycle in parallel and independent of the CPU activity.

Features

  • CORE
    • High-performance, low-power, TMS320C55x fixed-point digital signal processor
      • 13.33 to 5ns Instruction cycle time
      • 75 to 200MHz Clock rate
      • One or two instructions executed per cycle
      • Dual multiply-and-accumulate units (Up to 450 Million Multiply-Accumulates per Second [MMACS])
      • Two Arithmetic and Logic Units (ALUs)
      • Three internal data or operand read buses and two write buses
      • Software-compatible with C55x devices
      • Industrial temperature devices available
    • 320KB of Zero-Wait State On-Chip RAM
    • 128KB of Zero Wait-State On-Chip ROM (4 Blocks of 16K x 16-Bit)
    • Tightly coupled FFT hardware accelerator
  • PERIPHERAL
    • One Universal Host-Port Interface (UHPI) with a 16-bit muxed address or data bus
    • Master and slave Multichannel Serial Ports Interface (McSPI) with three chip selects
    • Master and slave Multichannel Buffered Serial Ports Interface (McBSP)
    • 16 and 8-Bit External Memory Interface (EMIF) with glueless interface
    • 3.84375M x 16-Bit Maximum Addressable External Memory Space (SDRAM or mSDRAM)
    • Universal Asynchronous Receiver/Transmitter (UART)
    • Device USB port with integrated 2.0 high-speed PHY
    • Direct Memory Access (DMA) controller
    • Three 32-Bit General-Purpose (GP) timers
    • Two MultiMedia Card and Secure Digital (eMMC, MMC, and SD) interfaces
    • Serial Port Interface (SPI) with four chip selects
    • Master and slave inter-integrated circuit (I2C Bus)
    • Three Inter-IC Sound (I2S Bus) modules for data transport
    • 10-Bit 4-input Successive Approximation (SAR) ADC
    • IEEE-1149.1 (JTAG) boundary-scan-compatible
    • Up to 26 GPIO pins (Multiplexed with other functions)
  • POWER
    • Four core isolated power supply domains: Analog, RTC, CPU and Peripherals, and USB
    • Four I/O isolated power supply domains: RTC I/O, EMIF I/O, USB PHY, and DVDDIO
    • 1.05V Core, 1.8, 2.75, or 3.3V I/Os
    • 1.3V Core, 1.8, 2.75, or 3.3V I/Os
    • 1.4V Core, 1.8, 2.75, or 3.3V I/Os
  • CLOCK
    • Real-Time Clock (RTC) with crystal input, separate clock domain, and power supply
    • Software-programmable Phase-Locked Loop (PLL) clock generator
  • BOOTLOADER
    • On-Chip ROM bootloader
  • PACKAGE
    • 196-Terminal Pb-Free plastic BGA (Ball Grid Array) (ZCH Suffix), 0.65mm pitch

Applications

  • Digital two-way radios
  • Low-power analytics applications (such as speech recognition, vision sensing, and fingerprint biometrics)
  • Voice applications (such as voice recorders, hands-free kits, and voice-enhancement subsystems)
  • Audio devices (such as echo-cancellation headphones and speakerphones or wireless headsets and microphones)
  • Portable medical devices

Functional Block Diagram

Block Diagram - Texas Instruments TMS320C5517 Fixed-Point Digital Signal Processor
發佈日期: 2018-10-15 | 更新日期: 2023-07-10