Nexperia 74LVC8T595 Translating Shift Registers
Nexperia 74LVC8T595 Translating Shift Registers are dual-supply 8-bit serial-in/serial or parallel-out shift registers with a storage register and three-state outputs. Fully specified from 1.1V to 5.5V, these low-power CMOS solutions are suitable for interfacing low-voltage MCUs with legacy peripherals. Both the shift and storage register feature separate clocks, and data is shifted on the positive-going transitions of the SHCP input. The data in the shift register is transferred to the storage register on a positive-going transition of the STCP input. If both clocks are connected together, the shift register is always one clock pulse ahead of the storage register. Nexperia 74LVC8T595 Translating Shift Registers include electrostatic discharge (ESD) protection.Features
- Wide supply voltage range
- VCC(A): 1.1V to 5.5V
- VCC(B): 1.1V to 5.5V
- High noise immunity
- Complies with JEDEC standards
- JESD8-12A (1.1V to 1.3V)
- JESD8-11A (1.4V to 1.6V)
- JESD8-7 (1.65V to 1.95V)
- JESD8-5 (2.3V to 2.7V)
- JESD8C (3.0V to 3.6V)
- JESD12-6 (4.5V to 5.5V)
- ESD protection
- HBM ANSI/ESDA/JEDEC JS-001 Class 3A exceeds 4000V
- CDM JESD22-C101E exceeds 1000 V
- Suspend mode
- Latch-up performance exceeds 100mA per JESD 78 Class II
- ±24mA output drive (VCC(A) = VCC(B) = 3.0V)
- Inputs accept voltages up to 5.5V
- IOFF circuitry provides partial Power-down mode operation
- Specified from -40°C to +85°C and -40°C to +125°C
Logic Diagram
Additional Resources
發佈日期: 2018-05-08
| 更新日期: 2023-03-15
