Tray Flip Flops

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Description Datasheet Availability Pricing (TWD) Filter the results in the table by unit price based on your quantity.
Qty. RoHS ECAD Model Logic Type
Logic Family
Number of Circuits
Output Type
Package / Case
Input Type
Polarity
Propagation Delay Time
High Level Output Current
Low Level Output Current
Supply Voltage - Min
Supply Voltage - Max
Mounting Style
Minimum Operating Temperature
Maximum Operating Temperature
Packaging

onsemi Flip Flops 3.3V/5V ECL Quad D-Type
Datasheet
87In Stock
Min.: 1
Mult.: 1

Flip-Flop 10 4 Circuit Differential LQFP-32 Single-Ended Inverting/Non-Inverting 0.6 ns - 3 V 5.5 V SMD/SMT - 40 C + 85 C Tray
onsemi Flip Flops 3.3V/5V ECL Quad D-Type
Datasheet
176In Stock
500Expected 8/25/2026
Min.: 1
Mult.: 1
Max.: 110

Flip-Flop 100 4 Circuit Differential LQFP-32 Single-Ended Inverting/Non-Inverting 0.6 ns - 3 V 5.5 V SMD/SMT - 40 C + 85 C Tray
onsemi Flip Flops 3.3V/5V ECL 6-Bit Diff w/Master Reset
Datasheet
39In Stock
Min.: 1
Mult.: 1

Differential Register 10 1 Circuit Differential LQFP-32 Differential Inverting/Non-Inverting 0.55 ns - 50 mA 50 mA - 3 V 5.5 V SMD/SMT - 40 C + 85 C Tray

onsemi Flip Flops 3.3V/5V ECL 6-Bit Diff w/Master Reset
Datasheet
250Expected 8/26/2026
Min.: 1
Mult.: 1

Differential Register 100 1 Circuit Differential LQFP-32 Differential Inverting/Non-Inverting 0.55 ns - 50 mA 50 mA - 3 V 5.5 V SMD/SMT - 40 C + 85 C Tray
Texas Instruments Flip Flops DIE SALE
Datasheet
Non-Stocked Lead-Time 26 Weeks
Min.: 100
Mult.: 100

HC CMOS Die CMOS 34 ns - 5.2 mA 5.2 mA 2 V 6 V 0 C + 25 C Tray
Texas Instruments Flip Flops DIE SALE
Datasheet
Non-Stocked Lead-Time 26 Weeks
Min.: 10
Mult.: 10

HC CMOS Die CMOS 34 ns - 5.2 mA 5.2 mA 2 V 6 V 0 C + 25 C Tray
Apogee Semiconductor Flip Flops LEO Dual D Flip-Flops and Registers w/Async Clear A-Grade NiPdAu TSSOP14 JEDEC tray
Datasheet
Non-Stocked Lead-Time 35 Weeks
Min.: 50
Mult.: 50
D Flip-Flop AP54RHC 2 Circuit Complementary TSSOP-14 - 24 mA 24 mA 1.65 VDC 5.5 VDC SMD/SMT - 55 C + 125 C Tray
Apogee Semiconductor Flip Flops LEO Dual D Flip-Flops and Registers w/Async Clear B-Grade NiPdAu TSSOP14 JEDEC tray
Datasheet
Non-Stocked Lead-Time 35 Weeks
Min.: 100
Mult.: 100
D Flip-Flop AP54RHC 2 Circuit Complementary TSSOP-14 - 24 mA 24 mA 1.65 VDC 5.5 VDC SMD/SMT - 55 C + 125 C Tray
Apogee Semiconductor Flip Flops LEO Dual D Flip-Flops and Registers w/Async Clear E-Grade NiPdAu TSSOP14 JEDEC tray
Datasheet
Non-Stocked Lead-Time 35 Weeks
Min.: 250
Mult.: 250
D Flip-Flop AP54RHC 2 Circuit Complementary TSSOP-14 - 24 mA 24 mA 1.65 VDC 5.5 VDC SMD/SMT - 55 C + 125 C Tray